This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to methods and apparatuses for providing full fault coverage for an integrated circuit thereby increasing product yield.
Integrated circuits are tested to determine the existence of defects which may introduce faults in the integrated circuit during use. Faults are typically mapped from physical faults to logical faults. Logical faults are distinguished on the basis of those faults which degrade performance and those faults which are fatal and completely stop the integrated circuit from working. After logic simulation of the integrated circuit is complete, fault simulation is conducted to see what happens when faults are deliberately introduced into the integrated circuit. Fault simulation is conducted using a set of test vectors which use inputs to the primary input pins of the integrated circuit to obtain predetermined outputs from the output pins of the integrated circuit.
Because of the complexity of the circuits, some of the circuits are inaccessible and cannot be tested regardless of the number of test vectors used. Other circuits may require a long and complicated test pattern sequence or high number of vectors to adequately test the circuit. As circuits become larger and more complex, the ability and economic feasibility of completely testing the circuits to find all detectable faults continues to decrease. Hence, fault models have been designed to provide a statistical number of faults in a circuit from the output data of the fault simulation tests. The term xe2x80x9cfault coveragexe2x80x9d is used to specify the ratio between the number of faults detectable and the total number of faults in the assumed fault universe for a circuit based on the fault model.
The number of potentially defective integrated circuits is determined from the fault coverage report. As the fault coverage value decreases, the number of undetected defective integrated circuits increases. Hence, there is a risk that a higher number of defective integrated circuits will be shipped than if all of the detectable faults had been detected by the simulation software. Shipping defective integrated circuits may result in returns which may have to be reprocessed and retested to determine the source of the failures. In the alternative, an additional fault testing tool may be used to increase the fault coverage. However, it is expected that such a tool will add considerable expense to integrated circuit production costs and result in only an incremental increase in the fault coverage. Thus there exists a need for a method for increasing the fault coverage without significantly increasing the production costs of integrated circuits.
The above and other needs are met by a method for increasing a fault coverage of an integrated circuit having a predetermined functionality. The method includes the steps of providing an integrated circuit layout on a substrate including functional units, free space and a first netlist, providing a fault grading report output including a number of unobserved faults and identified undetected nodes, providing a priority task list of key undetected nodes from the identified undetected nodes, selecting key undetected nodes to be covered with logic functions, selecting multi-unit sites in the free space adjacent the key undetected nodes to provide a locations list for the logic functions for connection to the key undetected nodes, generating a second netlist including the locations list for the logic functions, generating a metallization design for the integrated circuit according to the second netlist, and running an integrated circuit simulation to determine if the predetermined desired functionality for the integrated circuit is achieved.
In another aspect, the invention provides a tool for increasing fault coverage of an integrated circuit. The tool includes a key nodes detection device for matching key nodes to a fault grading report list of undetected nodes, a multi-sites selection device for reading a layout file of available multi-unit sites for the integrated circuit, a site matching device for matching available multi-unit sites to key undetected nodes, and a netlist generation device for building logic functions in the available multi-unit sites for connection to the key undetected nodes. The tool also builds circuitry to enable access to the nodes.
An advantage of the invention is that it enables use of existing substrate area for improving fault coverage of an integrated circuit without significantly increasing the layout congestion of the integrated circuit. Another advantage of the invention is that it provides a method and tool for achieving up to 100% fault coverage of an integrated circuit layout for an integrated circuit having sufficient free space adjacent undetected nodes. Still another advantage of the invention is that the tool for increasing fault coverage may be used before or after metallization of the substrate. The methods and apparatus of this invention may be applied to a wide variety of integrated circuits to reduce the number of faulty parts shipped to customers.